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? semiconductor components industries, llc, 2006 september, 2006 ? rev. 7 1 publication order number: cs5233 ? 3/d cs5233?3 500 ma and 1.5 a, 3.3 v dual input linear regulator with auxiliary control the cs5233 ? 3 provides a glitch ? free 3.3 v output from one of three possible supplies, (v in , v sb and 3.3 v aux ). an on ? chip linear regulator powers the output when either v in or v sb is available. otherwise auxdrv turns on an external pfet, which connects the 3.3 v aux supply to the output. the cs5233 ? 3 is intended to provide power to an asic on a pci network interface card (nic), and meets intel?s ?instantly available? power requirements which follow from the advanced configuration and power interface (acpi) standards. other applications include desktop computers, power supplies with multiple input sources, and pcmcia interface cards. the cs5233 ? 3 linear regulator provides a fixed 3.3 v output at up to 1.5 a with an overall accuracy of 2%. the internal npn ? pnp composite pass transistor provides a low dropout voltage and requires less supply current than a straight pnp design. full protection with both current limit and thermal shutdown is provided. designed for low reverse current, the ic prevents excessive current from flowing from v out to either v in or ground when the regulator input voltage is lower than the output. the auxiliary drive control feature allows the use of an external pfet to supply power to the output when the regulator supplies are off. the cs5233 ? 3 regulator is available in two package types: the 5 lead d 2 pak package (to ? 263) and soic ? 8 with 4 lead fused (df8) package. when powered from the v in source, the d 2 pak ? 5 is rated for 1.5 a and the soic ? 8 is rated for 500 ma. both packages are rated for 500 ma when only powered from the v sb source. features ? linear regulator ? 3.3 v 2% output voltage ? current limit ? thermal shutdown with hysteresis ? 400 a reverse current ? esd protected ? system power management ? auxiliary supply control ? ?glitch free? transition between 3 sources ? similar to cs5231 ? 3 ? high output current capability ? 1.5 a d 2 pak ? 5 ? 500 ma soic ? 8 df8 ? internally fused leads in soic ? 8 package http://onsemi.com pin connections and marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ? ordering information cs5233 ? 3gdp5 d 2 pak ? 5 50 units/rail cs5233 ? 3gdpr5 d 2 pak ? 5 750 tape & reel cs5233 ? 3gdf8 soic ? 8 95 units/rail cs5233 ? 3gdfr8 soic ? 8 2500 tape & reel soic ? 8 d suffix case 751 pin 1. v sb 2. v in 3. gnd 4. v out 5. auxdrv d 2 pak ? 5 dp suffix case 936ac cs5233 ? 3 awlyww 1 1 5 gnd auxdrv 1 5233 ? alyw3 8 gnd v out gnd v in gnd v sb 1 8 ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d.
cs5233 ? 3 http://onsemi.com 2 + + + +3.3 v aux v sb v in gnd 10 f min esr < 1.0 10 f min esr < 1.0 10 f min esr < 1.0 v sb v in gnd auxdrv v out cs5233 ? 3 asic v dd ds g figure 1. application diagram, 5.0 v to 3.3 v dual input regulator with auxiliary pfet power switch absolute maximum ratings* rating value unit operating junction temperature 150 c lead temperature soldering: reflow: (smd styles only) (note 1) 230 peak c storage temperature range ? 65 to +150 c esd susceptibility (human body model) 2.0 kv 1. 60 second maximum above 183 c. *the maximum package power dissipation must be observed. absolute maximum ratings pin name pin symbol v max v min i source i sink ic power input (main) v in 6.0 v ? 0.3 v 100 ma internally limited ic power input (standby) v sb 6.0 v ? 0.3 v 100 ma internally limited output voltage v out 6.0 v ? 0.3 v internally limited 100 ma auxiliary drive output auxdrv 6.0 v ? 0.3 v 10 ma 50 ma ic ground gnd n/a n/a n/a n/a electrical characteristics (0 c < t a < 70 c; 0 c < t j < 150 c; 4.75 v < v in ; v sb < 6.0 v; c out 10 f with esr < 1.0 , i out = 10 ma; unless otherwise specified.) characteristic test conditions min typ max unit linear regulator output voltage 10 ma < i out < i max . (note 2) 3.234 ? 2% 3.3 3.366 + 2% v line regulation i out = 10ma; v source = 4.75 v to 6.0 v. (note 3) ? 1.0 5.0 mv load regulation v source = 5.0 v; i out = 10 ma to i max . (notes 2, 3) ? 5.0 15 mv 2. i max = 1.5 a for d 2 pak ? 5 only and with v in > 4.75 v, otherwise i max = 500 ma. 3. applies to either v in or v sb .
cs5233 ? 3 http://onsemi.com 3 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 150 c; 4.75 v < v in ; v sb < 6.0 v; c out 10 f with esr < 1.0 , i out = 10 ma; unless otherwise specified.) characteristic unit max typ min test conditions linear regulator ground current i out = 10 ma i out = 500 ma i out = 1.5 a (note 4) ? ? ? 2.0 3.0 9.0 3.0 6.0 20 ma ma ma reverse current v source = 0 v; v out = 3.3 v (note 4) ? 0.4 1.0 ma current limit v in input soic ? 8 d 2 pak ? 5 0 v < v out < 3.2 v v in > 4.25 v 0.55 1.6 0.8 2.4 1.3 4.5 a a current limit v sb input either package 0 v < v out < 3.2 v; v in < 4.25 v; v sb > 4.25 v 0.55 0.8 1.3 a thermal shutdown (note 5) 150 180 210 c thermal shutdown hysteresis (note 5) ? 25 ? c auxiliary drive v in turn ? on threshold v sb = 0 v; ramp v in up until auxdrv goes high and regulator turns on 4.35 4.5 4.65 v v in turn ? off threshold v sb = 0 v; ramp v in down until auxdrv goes low and regulator turns off 4.25 4.4 4.55 v v sb turn ? on threshold v sb = 0 v; ramp v sb up until auxdrv goes high and regulator turns on 4.35 4.5 4.65 v v sb turn ? off threshold v sb = 0 v; ramp v sv down until auxdrv goes low and regulator turns off 4.25 4.4 4.55 v threshold hysteresis ? 75 100 125 mv auxdrv peak voltage v out = 0 v; 0 v < v source < 2.0 v (note 4) v out = 0 v; i auxdrv = 100 a; 2.0 v < v in < 4.25 v; 2.0 v < v sb < 4.25 v v out = 3.0 v; i auxdrv = 100 a; 0 v < v in < 4.25 v; 0 v < v sb < 4.25 v ? ? ? 0.4 0.1 0.1 1.8 0.4 0.4 v v v auxdrv high voltage v in or v sb > 4.65 v 3.75 4.0 ? v auxdrv pin current limit v auxdrv = 1.0 v; v source = 4.0 (note 4) 0.5 6.0 25 ma v auxdrv turn ? off response time step v source from 4.0 v to 5.0 v (notes 4, 5) ? 20 40 s v auxdrv turn ? on response time step v source from 5.0 v to 4.0 v (notes 4, 5) ? 1.0 10 s pull ? up resistance v in = 0 v and v in > 4.7 v (notes 4, 5) 5.0 10 25 k 4. applies to either v in or v sb . 5. guaranteed by design, not 100% production tested.
cs5233 ? 3 http://onsemi.com 4 package pin description package lead # lead symbol function d 2 pak ? 5 soic ? 8 narrow 1 1 v sb standby 5.0 v input voltage. 2 2 v in 5.0 v main input voltage. 3, tab 5, 6, 7, 8 gnd ground and ic substrate connection. 4 3 v out regulated output voltage. 5 4 auxdrv control voltage for the external pfet switched auxiliary supply. this pin drives low if v in and v sb are less than 4.4 v (typical), otherwise it is pulled up to the greater of v in or v sb through an internal diode and 10 k resistor. v in uv comparator v in v sb auxdrv v sb uv comparator internal bias bandgap reference thermal shutdown error amplifier enable enable current limit v out gnd ? + + ? + ? figure 2. block diagram
cs5233 ? 3 http://onsemi.com 5 typical performance characteristics figure 3. output voltage vs. junction temperature, output voltage when powered by v in or v sb junction temperature ( c) 3.310 3.305 3.300 3.295 120 0 3.290 output voltage (v) 100 80 60 40 20 i out (a) 3.5 0 v out (v) 0.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 figure 4. output voltage vs. load current, v sb values taken with v in = 0 v load current (a) 3.5 0 ground current (ma) 0.25 3.0 2.5 2.0 1.5 0.50 0.75 1.00 1.25 1.50 v sb = 5.0 v v in = 5.0 v figure 5. ground pin current vs. output current, v sb data with v in = 0 v v in = 5.0 v v sb = 5.0 v junction temperature ( c) 460 0 reverse current ( a) 20 440 420 40 60 80 100 120 figure 6. reverse current vs. junction temperature v out output current figure 7. transient load response, transient response for 1.5 a step load, v in = 5.0 v, c out = 33 f @ 0.4 esr v in auxdrv 5.0 4.0 figure 8. auxdrv response time
cs5233 ? 3 http://onsemi.com 6 junction temperature ( c) 4.52 4.50 4.48 4.46 120 0 4.38 v in threshold voltage (v) 100 80 60 40 20 4.44 4.42 4.40 v in turn ? on threshold v in turn ? off threshold figure 9. v in threshold vs. junction temperature, typical minimum and maximum threshold voltages to switch auxdrv control junction temperature ( c) 4.5 120 0 4.3 auxdrv high voltage (v) 100 80 60 40 20 4.4 v in = 4.65 v figure 10. auxdrv high voltage vs. junction temperature input voltage (v) 4.0 0 0 auxdrv voltage (v) 4.0 2.0 2.0 125 c 4.5 27 c 0 c figure 11. auxdrv voltage vs. input voltage (v sb or v in ) at three temperatures
cs5233 ? 3 http://onsemi.com 7 applications information input and output voltage matrix input outputs v in ? 5 ? 8 0 v theory of operation linear regulator the cs5233 ? 3 is a dual input fixed 3.3 v linear regulator that contains an auxiliary drive control feature. when v in alone is present, or v in and v sb are simultaneously present, the cs5233 ? 3 uses the v in supply to generate the 3.3 v output at currents of up to 1.5 a. when v sb alone is present, the cs5233 ? 3 uses the v sb supply to generate the 3.3 v output at currents of up to 500 ma. the linear regulator is composed of a composite pnp ? npn pass transistor to provide low ? voltage dropout capabil ity. an output capacitor greater than 10 f with equivalent series resistance (esr) less than 1.0 is required for compensation. more information is provided in the stability considerations section. auxiliary drive feature the cs5233 ? 3 provides an auxiliary drive feature that allows a load to remain powered even if both supplies to the ic are absent. an external p ? channel fet is the only additional component required to implement this function when the auxiliary power supply is available. the pfet gate is connected to the ic?s auxdrv output, the pfet drain is connected to the auxiliary power supply, and the pfet source is connected to the load. the polarity of this connection is very important, since the pfet body diode will be connected between the load and the auxiliary supply. if the pfet is connected with its drain to the load and its source to the supply, the body diode could be forward ? biased if the auxiliary supply is not present. this would result in the linear regulator providing current to everything on the auxiliary supply rail. the auxdrv (5.0 v detect) output is pulled up to the input voltage through an internal resistor when v in or v sb are available. if v in and v sb are not available or both drop below 4.4 v, the auxdrv output goes low, turning on an external pfet that connects the 3.3 v auxiliary supply to the load. the auxdrv is low only when neither v in nor v sb are available. there is 100 mv of hysteresis (typical) in the circuitry that determines if v in or v sb are present. stability considerations the output capacitor helps determine three main characteristics of a linear regulator: loop stability, load transient response, and start ? up delay. the cs5233 ? 3 is designed to be stable with an output capacitor that has a minimum value of 10 f and an equivalent series resistance less than 1.0 . to guarantee loop stability, the output capacitor should be located close to the regulator output and ground pins. the load transient response, during the time it takes the regulator to respond, is also determined by the output capacitor. for large changes in load current, the esr of the output capacitor causes an immediate drop in output voltage given by: v i esr there is then an additional drop in output voltage given by: v i t c where t is the time for the regulation loop to begin to respond, (typically 4.0 s for the cs5233 ? 3). if tight output regulation is required with fast changing loads, a capacitor network of tantalum and low esr ceramic capacitors can be added as close to the load as possible, with enough capacitance and a reduced esr to minimize the voltage change, as determined by the formulas above. input capacitors and the vin thresholds a capacitor placed on the v in pin will help to improve transient response. during a load transient, the input capacitor serves as a charge ?reservoir,? providing the needed extra current until the external power supply can
cs5233 ? 3 http://onsemi.com 8 respond. one of the consequences of providing this current is an instantaneous voltage drop at v in due to capacitor esr. the magnitude of the voltage change is again the product of the current change and the capacitor esr. it is very important to consider the maximum current step that can exist in the system. if the change in current is large enough, it is possible that the instantaneous voltage drop on v in will exceed the v in threshold hysteresis, and the ic will enter a mode of operation resembling an oscillation. as the part turns on, the output current i out will increase, reaching current limit during initial charging. increasing i out results in a drop at v in such that the shutdown threshold is reached. the part will turn off, and the load current will decrease. as i out decreases, v in will rise and the part will turn on, starting the cycle all over again. this oscillatory operation is most likely at initial start ? up when the output capacitance is not charged, and in cases where the ramp ? up of the v in supply is slow. it may also occur during the power transition when the linear regulator turns on and the pfet turns off. a 20 s delay exists between turn ? on of the regulator and the auxdrv pin pulling the gate of the pfet high. this delay prevents ?chatter? during the power transitions. if required, using a few capacitors in parallel to increase the bulk charge storage and reduce the esr should give better performance than using a single input capacitor. short, straight connections between the power supply and v in lead along with careful layout of the pc board ground plane will reduce parasitic inductance effects. wide v in and v out traces will reduce resistive voltage drops. choosing the pfet switch the choice of the external pfet switch is based on two main considerations. first, the pfet should have a very low turn ? on threshold. choosing a switch transistor with v gs(on) 1.0 v will ensure the pfet will be fully enhanced with only 3.3 v of gate drive voltage. second, the switch transistor should be chosen to have a low r ds(on) to minimize the voltage drop due to current flow in the switch. the formula for calculating the maximum allowable on ? resistance is r ds(on)max v aux(min) v out(min) 1.5 i out(max) v aux(min) is the minimum value of the auxiliary supply voltage, v out(min) is the minimum allowable output voltage, i out(max) is the maximum output current and 1.5 is a ?fudge factor? to account for increases in r ds(on) due to temperature. output voltage sensing it is not possible to remotely sense the output voltage of the c5233 ? 3 since the feedback path to the error amplifier is not externally available. it is important to minimize voltage drops due to metal resistance of high current pc board traces. such voltage drops can occur in both the supply traces and the return traces. the following board layout practices will help to minimize output voltage errors: ? always place the linear regulator as close to both load and output capacitors as possible. ? always use the widest possible traces to connect the linear regulator to the capacitor network and to the load. ? connect the load to ground through the widest possible traces. ? connect the ic ground to the load ground trace at the point where it connects to the load. current limit the cs5233 ? 3 has internal current limit protection. output current is limited to a typical value of 3.0 a for the d 2 pak using v in and 800 ma using v sb , even under output short circuit conditions. if the load current drain exceeds the current limit value, the output voltage will be pulled down and will result in an out of regulation condition. thermal shutdown the cs5233 ? 3 has internal temperature monitoring circuitry. the output is disabled if junction temperature of the ic reaches 180 c. thermal hysteresis is typically 25 c and allows the ic to recover from a thermal fault without the need for an external reset signal. the monitoring circuitry is located near the composite pnp ? npn output transistor, since this transistor is responsible for most of the on ? chip power dissipation. the combination of current limit and thermal shutdown will protect the ic from nearly any fault condition. reverse current protection during normal system operation, the auxiliary drive circuitry will maintain voltage on the v out pin. ic reliability and system efficiency are improved by limiting the amount of reverse current that flows from v out to ground and from v out to v in . current flows from v out to ground through the feedback resistor divider that sets up the output voltage, typically 400 a. current flow from v out to v in will be limited to leakage current after the ic shuts down. on ? chip rc time constants are such that the output transistor should be turned off well before v in drops below the v out voltage. calculating power dissipation and heatsink requirements most linear regulators operate under conditions that result in high on ? chip power dissipation. this results in high junction temperatures. since the ic has a thermal shutdown feature, ensuring the regulator will operate correctly under normal conditions is an important design consideration. some heatsinking will usually be required. thermal characteristics of an ic depend on four parameters: ambient temperature (t a in c), power dissipation (p d in watts), thermal resistance from the die to
cs5233 ? 3 http://onsemi.com 9 the ambient air ( ja in c per watt) and junction temperature (t j in c). the maximum junction temperature is calculated from the formula below: t j(max) t a(max) ja p d(max) maximum ambient temperature and power dissipation are determined by the design, while ja is dependent on the package manufacturer . the maximum junction temperature for operation of the cs5233 ? 3 within specification is 150 c. the maximum power dissipation of a linear regulator is given as p d(max) (v in(max) v out(min) ) i load(max) v in(max) i gnd(max) where i gnd(max) is the ic bias current. it is possible to change the effective value of ja by adding a heatsink to the design. a heatsink serves in some manner to raise the ef fective area of the package, thus improving the flow of heat from the package into the surrounding air. each material in the path of heat flow has its own characteristic thermal resistance, all measured in c per watt. the thermal resistances are summed to determine the total thermal resistance between the die junction and air. there are three components of interest: junction ? to ? case thermal resistance ( jc ), case ? to ? heatsink thermal resistance ( cs ) and heatsink ? to ? air thermal resistance ( sa ). the resulting equation for junction ? to ? air thermal resistance is ja jc cs sa ,or ja jc sa for cs 0 the value of jc for the cs5233 ? 3 is provided in the packaging information section of this data sheet. cs can be considered zero, since heat is conducted out of the package by the ic leads and the tab of the d 2 pak package, and since the ic leads and tab are soldered directly to the pc board. modification of sa is the primary means of thermal management. for surface mount components, this means modifying the amount of trace metal that connects to the ic. the thermal capacity of pc board traces is dependent on how much copper area is used, if the ic is in direct contact with the metal, whether the metal surface is coated with some type of sealant, and whether there is airflow across the pc board. the chart provided below shows heatsinking capability of a square, single sided copper pc board trace. the area is given in square millimeters, and it is assumed there is no airflow across the pc board. figure 12. thermal resistance capability of copper pc board metal traces pc board trace area (mm 2 ) 70 0 thermal resistance, cw 2000 50 60 40 30 20 10 0 4000 6000
cs5233 ? 3 http://onsemi.com 10 package dimensions d 2 pak ? 5 dp suffix case 936ac ? 01 issue o for d 2 pak outline and dimensions ? contact factory
cs5233 ? 3 http://onsemi.com 11 package dimensions soic ? 8 df suffix case 751 ? 07 issue aa seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m figure 13. soic ? 8 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 soldering footprint package thermal data parameter d 2 pak ? 5 soic ? 8 unit r jc typical 1.0 ? 4.0 25 c/w r ja typical 10 ? 50* 110 c/w *depending on thermal properties of substrate. r ja = r jc + r ca .
cs5233 ? 3 http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 cs5233 ? 3/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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